PROJECTS | resume

LATEST PROJECTS

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Project | 01 Dataflow Accelerator

Design Multi-pumped Mult-ported Ram by using M20K memory blocks and connect it to floating point DSP hard IP core in Altera Arria 10 FPGAs to form one tile. Multiple such tiles are instantiated and connected through Network on Chip (NoC) by proper floor planning to achieve maximum operating frequency and minimum ALM utilization.

Project | 02 Audio Processing & Spectrum Analysis

Implementation and Optimization of FFT (Fast Fourier Transform) module, Noise module, Sliding window averaging module, Squaring module & Threshold module. Verilog and C were used extensively for programming on ARM and Xilinx FPGA of Zedboard.

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Project | 03 Deep Learning Algorithm implementation on TI DSP (TMS 320C6678)

Implementation and Optimization of Deep Learning algorithm (for Computer Vision) using ImageLib & OpenCV library on TI DSP and Code Composer Studio IDE in C .